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顯示項目 544811-544820 / 2348971 (共234898頁)
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| 國立臺灣科技大學 |
2004 |
Layout Improvement for Wafer Fabrication Plants
|
Chen, J. C. ; Yang, R. T. ; Peng, K. M. ; Wang, C. C. |
| 中原大學 |
2004-03 |
Layout Improvement for Wafer Fabrication Plants
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J. C. Chen;R. T. Yang;K. M. Peng;C. C. Wang; |
| 臺大學術典藏 |
2022-09-21T23:30:15Z |
Layout of 1.50-inch, 3207-ppi oled display with oslsi/silsi structure capable of division driving fabricated through vlsi process with side-by-side patterning by photolithography
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Saito, Toshihiko; Mizuguchi, Toshiki; Okamoto, Yuki; Ito, Minato; Toyotaka, Kouhei; Kozuma, Munehiro; Matsuzaki, Takanori; Kobayashi, Hidetomo; Onuki, Tatsuya; Hiura, Yoshikazu; Hodo, Ryota; Sasagawa, Shinya; Kunitake, Hitoshi; Nakamura, Daiki; Sato, Hitomi; Kimura, Hajime; Wu, Chih Chiang; Yoshida, Hiroshi; Chen, Min Cheng; MING-HAN LIAO; Chang, Shou Zen; Yamazaki, Shunpei |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:51Z |
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces
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Chang, WJ; Ker, MD |
| 中原大學 |
1998-11-10 |
Layout structure for improving resistance uniformity of a polysilicon resistor
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Shen-Wen Cheng;Chun-Lin Cheng |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process
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Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 1:Computer-Aided VLSI Routing Design
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Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985 |
Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design
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Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 3:Design and Implementation of a Design Rule Checking System for VLSI Design
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Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
顯示項目 544811-544820 / 2348971 (共234898頁)
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