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顯示項目 634241-634250 / 2348973 (共234898頁)
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| 臺大學術典藏 |
2007 |
On-Chip Bus Architecture Optimization for Multi-core SoC Systems
|
Chen, Ya-Shu; Shih, Chi-Sheng; Lien, Cheng-Min; Chen, Ya-Shu; Shih, Chi-Sheng; Lien, Cheng-Min |
| 臺大學術典藏 |
2018-09-10T06:30:38Z |
On-chip bus architecture optimization for multi-core SoC systems
|
CHI-SHENG SHIH; Shih, C.-S.; Lien, C.-M.; Chen, Y.-S. |
| 臺大學術典藏 |
2020-05-04T07:44:32Z |
On-Chip Bus Architecture Optimization for Multi-core SoC Systems.
|
Lien, Cheng-Min; Chen, Ya-Shu; Shih, Chi-Sheng; CHI-SHENG SHIH |
| 國立交通大學 |
2014-12-08T15:25:38Z |
On-chip bus encoding for LC cross-talk reduction
|
Huang, JS; Tu, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:16:40Z |
On-chip bus encoding for power minimization under delay constraint
|
Lin, Tzu-Wei; Tu, Shang-Wei; Jou, Jing-Yang |
| 國立交通大學 |
2019-04-02T05:58:45Z |
On-Chip Cell Incubator for Simultaneous Observation of Culture with and without Periodic Hydrostatic Pressure
|
Horade, Mitsuhiro; Tsai, Chia-Hung Dylan; Kaneko, Makoto |
| 國立交通大學 |
2017-04-21T06:49:46Z |
On-chip compensated error amplifier for fast transient DC-DC converters
|
Huang, Hong-Wei; Ho, Hsin-Hsin; Chang, Chia-Jung; Chen, Ke-Horng; Kuo, Sy-Yen |
| 臺大學術典藏 |
2018-09-10T06:02:22Z |
On-Chip Compensated Error Amplifier for Fast Transient DC-DC Converters
|
H. W. Huang; H. H. Ho; C. J. Chen; K. H. Chen; S. Y. Kuo; SY-YEN KUO |
| 國立成功大學 |
2008 |
On-chip counting the number and the percentage of CD4+T lymphocytes
|
Wang, Yao-Nan; Kang, Yuejun; Xu, Dongyan; Chon, Chan Hee; Barnett, Louise; Kalams, Spyros A.; Li, Deyu; Li, Dongqing |
| 國立交通大學 |
2014-12-08T15:25:05Z |
On-chip DC-DC converter with frequency detector for dynamic voltage scaling technology
|
Yang, Jen-Wei; Huang, Po-Tsang; Hwang, Wei |
顯示項目 634241-634250 / 2348973 (共234898頁)
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