| 臺大學術典藏 |
2020-06-11T06:25:37Z |
Design and analysis of a 0.877.5-GHz ultra-broadband distributed drain mixer using 0.13-μm CMOS technology
|
Yang, H.-Y.;Tsai, J.-H.;Wang, C.-H.;Lin, C.-S.;Lin, W.-H.;Lin, K.-Y.;Huang, T.-W.;Wang, H.; Yang, H.-Y.; Tsai, J.-H.; Wang, C.-H.; Lin, C.-S.; Lin, W.-H.; Lin, K.-Y.; Huang, T.-W.; Wang, H.; KUN-YOU LIN |
| 元智大學 |
2009-03 |
Design and analysis of a 0.877.5-GHz ultra-broadband distributed drain mixer using 0.13-弮m CMOS technology
|
蔡政翰; Hong-Yuan Yang; Chi-Hsueh Wang; Chin-Shen Lin; Wei-Heng Lin; Kun-You Lin; Tian-Wei Huang; Huei Wang |
| 國立臺灣大學 |
2009 |
Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13-$mu$m CMOS Technology
|
Yang, Hong-Yuan; Tsai, Jeng-Han; Wang, Chi-Hsueh; Lin, Chin-Shen; Lin, Wei-Heng; Lin, Kun-You; Huang, Tian-Wei; Yang, Huei Hong-Yuan; Tsai, Jeng-Han; Wang, Chi-Hsueh; Lin, Chin-Shen; Lin, Wei-Heng; Lin, Kun-You; Huang, Tian-Wei; Wang, Huei |
| 國立臺灣大學 |
1999 |
Design and Analysis of a 2-D Eigenspace-Based Interference Canceller
|
Lee, Cheng-Chou; Lee, Ju-Hong |
| 臺大學術典藏 |
2018-09-10T07:41:31Z |
Design and Analysis of a 2-D Eigenspace-Based Interference Canceller
|
C.-C. Lee; Ju-Hong Lee; JU-HONG LEE |
| 國立交通大學 |
2017-04-21T06:48:52Z |
Design and Analysis of a 2-DOF Planar Nano-positioner with Low Parasitic Rotation
|
Lin, Hung-Ruei; Hung, Shao-Kang; Cheng, Chiao-Hua |
| 國立臺灣大學 |
2005-06 |
Design and analysis of a 20-GHz clock multiplication unit in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Wu, Shanghann |
| 臺大學術典藏 |
2018-09-10T05:29:28Z |
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
|
Jri Lee; Shanghann Wu; JRI LEE |
| 國立暨南國際大學 |
2012 |
Design and Analysis of a 21-29-GHz Ultra-Wideband Receiver Front-End in 0.18-mu m CMOS Technology
|
Huang, SL; Huang, SL |
| 國立暨南國際大學 |
2012 |
Design and Analysis of a 21-29-GHz Ultra-Wideband Receiver Front-End in 0.18-mu m CMOS Technology
|
李仁豪?; Lee, JH |
| 國立暨南國際大學 |
2012 |
Design and Analysis of a 21-29-GHz Ultra-Wideband Receiver Front-End in 0.18-mu m CMOS Technology
|
林佑昇; Lin, YS |
| 國立暨南國際大學 |
2012 |
Design and Analysis of a 21-29-GHz Ultra-Wideband Receiver Front-End in 0.18-mu m CMOS Technology
|
Wang, CC; Wang, CC |
| 國立暨南國際大學 |
2012 |
Design and Analysis of a 21-29-GHz Ultra-Wideband Receiver Front-End in 0.18-mu m CMOS Technology
|
Wang, CH; Wang, CH |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers
|
Jeng-Han Tsai; Hong-Yeh Chang; Pei-Si Wu; Yi-Lin. Lee; Tian-Wei Huang; Huei Wang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers
|
Jeng-Han Tsai; Hong-Yeh Chang; Pei-Si Wu; Yi-Lin. Lee; Tian-Wei Huang; Huei Wang |
| 國立臺灣大學 |
2006 |
Design and Analysis of a 44-GHz MMIC Low-loss Built-in Linearizer for High-Linearity Medium Power Amplifiers
|
Tsai, Jeng-Han; Chang, Hong-Yeh; Wu, Pei-Si; Lee, Yi-Lin; Huang, Tian-Wei; Wang, Huei |
| 臺大學術典藏 |
2018-09-10T06:03:10Z |
Design and Analysis of a 44-GHz MMIC Low-loss Built-in Linearizer for High-Linearity Medium Power Amplifiers
|
Jeng-Han Tsai; Hong-Yeh Chang; Pei-Si Wu; Yi-Lin Lee; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design and Analysis of A 55 to 71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process
|
Yung-Nien Jen; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang |
| 國立臺灣大學 |
2009 |
Design and analysis of a 55 to 71-GHz compact and broadband distributed active transformer power amplifier in 90-nm CMOS process
|
Jen, Yung-Nien; Tsai, Jeng-Han; Huang, Tian-Wei; Wang, Huei |
| 臺大學術典藏 |
2018-09-10T07:37:10Z |
Design and Analysis of a 55–71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process
|
HUEI WANG; Yung-Nien Jen;Jeng-Han Tsai;Tian-Wei Huang;Huei Wang; Yung-Nien Jen; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:16Z |
Design and Analysis of A 77.3 % Locking Range Divide-by-4 Frequency Divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei Huang; TIAN-WEI HUANG |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
|
Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang |
| 亞洲大學 |
2016 |
Design and Analysis of a 90V Microwave P-I-N Diode Switches & Design of High performance UMOSFETs for power switching Application
|
Imam, Syed Sarwar |
| 國立臺灣大學 |
2002 |
Design and Analysis of a Backbone Architecture with TDMA Mechanism for IP Optical Networking
|
Chang, Chi-Yuan; Kuo, Sy-Yen |
