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Showing items 315671-315680 of 2348674 (234868 Page(s) Totally)
<< < 31563 31564 31565 31566 31567 31568 31569 31570 31571 31572 > >>
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| 國立交通大學 |
2014-12-08T15:38:45Z |
Design on ESD protection scheme for IC with power-down-mode operation
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2019-04-02T06:04:44Z |
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications
|
Ker, Ming-Dou; Wu, Chien-Hua |
| 義守大學 |
2015-06 |
Design on MEMS-based 3D biochip for drug-released dispenser
|
Hsiang-Chen Hsu;Li-Ming Chu;Baojun Liu;Chien-Yuan Lai |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications
|
Ker, MD; Chen, SL; Tsai, CS |
| 國立交通大學 |
2014-12-08T15:16:38Z |
Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability
|
Ker, Ming-Dou; Hu, Fang-Ling |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
|
Chen, Zi-Ping; Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, Ming-Dou; Chen, Wen-Yi; Hsu, Kuo-Chun |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, MD; Chen, WY; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:43:10Z |
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
|
Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:45:27Z |
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
|
Ker, MD; Lo, WY |
Showing items 315671-315680 of 2348674 (234868 Page(s) Totally)
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