| 國立交通大學 |
2014-12-08T15:24:49Z |
Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
|
Chen, Zi-Ping; Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, Ming-Dou; Chen, Wen-Yi; Hsu, Kuo-Chun |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, MD; Chen, WY; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:43:10Z |
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
|
Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:45:27Z |
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
|
Ker, MD; Lo, WY |
| 國立屏東大學 |
2011 |
Design optimal control of ship maneuver patterns for conllision avoidance : a review
|
陳震遠;C.H.Shih;Huang, Po-Hsuan;Yamamura, Saburo |
| 淡江大學 |
2009-10 |
Design Optimization and Analysis Applying DOE for Intake and Exhaust Pipeline of a Motorcycle
|
史建中 |
| 義守大學 |
2016-01 |
Design Optimization and Implementation of Genetic-Based Moving Sliding Manifold Strategy for Parallel Operation of DC-AC Converters
|
En-Chih Chang;Hairong Wang;Kuo-Yuan Liao;Rong-Ching Wu |
| 國立臺灣科技大學 |
2017 |
Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly
|
Fang, S.-Y;Hong, Y.-X. |
| 國立臺灣科技大學 |
2017 |
Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly
|
Lin, K.-L.;Fang, S.-Y.;Hong, Y.-X. |
| 臺大學術典藏 |
2021-09-14T23:19:16Z |
Design optimization for ADMM-Based SVM Training Processor for Edge Computing
|
Huang, Shuo An; Hsieh, Yi Yen; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2022-04-25T06:41:37Z |
Design optimization for ADMM-Based SVM Training Processor for Edge Computing
|
Huang S.-A;Hsieh Y.-Y;Yang C.-H.; Huang S.-A; Hsieh Y.-Y; Yang C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2000 |
Design optimization for an LPG automobile engine
|
Jaw, Shenq-Yuh; Wu, Tzann-Dwo;Chen, Yih-Nan;Yen, Jia-Yush;Jaw, Shenq-Yuh; Wu, Tzann-Dwo; Chen, Yih-Nan; Yen, Jia-Yush |
| 國立臺灣大學 |
2000 |
Design optimization for an LPG automobile engine
|
Wu, Tzann-Dwo; Chen, Yih-Nan; Yen, Jia-Yush; Jaw, Shenq-Yuh |
| 臺大學術典藏 |
2018-09-10T04:33:06Z |
Design optimization for asymmetrical ZVS-PWM Zeta converter
|
Wu, T.-F.; Liang, S.-A.; Chen, Y.-M.; YAOW-MING CHEN |
| 國立臺灣科技大學 |
2009-11-02 |
Design Optimization for Cogging Torque Minimization and Efficiency Maximization of a High-speed PM Motor
|
Hwang, Chang-Chou; Chang, Chia-Ming; Li, Ping-Lun |
| 臺大學術典藏 |
1993 |
Design optimization for high power and high speed surface-emitting lasers
|
Gamelin, J;Lin, J;Lau, KY;Hong, M;Mannaerts, JP; Gamelin, J; Lin, J; Lau, KY; Hong, M; Mannaerts, JP; MINGHWEI HONG |
| 修平科技大學 |
2005 |
Design Optimization for Pin-Fin Heat Sinks
|
Chen, H. T.;Chen, P. L.;Horng, J. T.;Hung, Y. H. |
| 臺大學術典藏 |
2019-07-03T07:15:32Z |
Design optimization for the hybrid power system of a green building
|
Wang F.-C.;Chen P.-J.; Chen P.-J.; Wang F.-C. |
| 國立臺灣科技大學 |
2015 |
Design optimization for ultrahigh efficiency buck regulator using wide bandgap devices
|
Lai, J.-S;Lin, C.-Y;Liu, Y.-C;Zhang, L;Zhao, X. |
| 國立交通大學 |
2015-07-21T08:31:14Z |
Design Optimization of 16-nm Bulk FinFET Technology via Geometric Programming
|
Su, Ping-Hsun; Li, Yiming |
| 國立交通大學 |
2018-08-21T05:56:36Z |
Design Optimization of a 1.4 GHz Low Power Bulk-Driven Mixer
|
Li, Chun-Hsing; Kuo, Chien-Nan |
| 臺大學術典藏 |
2020-08-05T02:45:34Z |
Design optimization of a 1.4 GHz low power bulk-driven mixer
|
Chun-Hsing Li;Chien-Nan Kuo;CHUN-HSING LI; Chun-Hsing Li; Chien-Nan Kuo; CHUN-HSING LI; CHUN-HSING LI |
| 臺大學術典藏 |
2020-02-26T01:36:45Z |
Design Optimization of a Compliant Revolute Joint
|
Wu, J.-M.;Shih, P.-J.;Lee, J.-J.Po-Jen Shih; Wu, J.-M.; Shih, P.-J.; Lee, J.-J.; PO-JEN SHIH |
| 國立交通大學 |
2014-12-08T15:42:07Z |
Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique
|
Li, Yiming; Li, Yih-Lang; Yu, Shao-Ming |
