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Showing items 437051-437060 of 2348719 (234872 Page(s) Totally) << < 43701 43702 43703 43704 43705 43706 43707 43708 43709 43710 > >> View [10|25|50] records per page
| 元智大學 |
2004-08 |
FPGA Implementation of an All-Digital T/2-Spaced QPSK Receiver with Farrow Interpolation Timing Synchronizer and Recursive Costas Loop
|
黃正光; C. H. Chu |
| 元智大學 |
2004-08 |
FPGA Implementation of an All-Digital T/2-Spaced QPSK Receiver with Farrow Interpolation Timing Synchronizer and Recursive Costas Loop
|
黃正光; C. H. Chu |
| 國立臺灣科技大學 |
2015 |
FPGA implementation of automatic speech recognition system in a car environment
|
Syu, D.-F;Syu, Syu S.-W;Ruan, S.-J;Huang, Y.-C;Yang, C.-K. |
| 國立臺灣科技大學 |
2016 |
FPGA implementation of automatic speech recognition system in a car environment
|
Syu, D.-F;Syu, Syu S.-W;Ruan, S.-J;Huang, Y.-C;Yang, C.-K. |
| 國立交通大學 |
2018-08-21T05:56:43Z |
FPGA Implementation of EEG System-on-Chip with Automatic Artifacts Removal based on BSS-CCA Method
|
Chou, Chia-Ching; Chen, Tsan-Yu; Fang, Wai-Chi |
| 南台科技大學 |
2005-06 |
FPGA Implementation of FIR Filter with smallest Processor
|
魏兆煌; C.H. Wei ; H.C. Hsiao ; S.W. Tsai |
| 中華大學 |
2011 |
FPGA Implementation of High Performance DCT/IDCT Processor
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2011 |
FPGA Implementation of High Performance DCT/IDCT Processor
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2005 |
FPGA Implementation of High-Speed 3-D Graphic Engine Using Double Rotation CORDIC Algorithm
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
FPGA Implementation of Image Scalar for LCD Monitor and TV Controller
|
宋志雲; Sung, Tze-Yun |
Showing items 437051-437060 of 2348719 (234872 Page(s) Totally) << < 43701 43702 43703 43704 43705 43706 43707 43708 43709 43710 > >> View [10|25|50] records per page
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