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Showing items 557616-557625 of 2348638 (234864 Page(s) Totally)
<< < 55757 55758 55759 55760 55761 55762 55763 55764 55765 55766 > >>
View [10|25|50] records per page
| 國立臺灣大學 |
2006 |
Low Power Scheduling Method using Multiple Supply Voltages
|
Tsai, Kun-Lin; Lee, Ju-Yueh; Ruan, Shanq-Jang; Lai, Feipei |
| 淡江大學 |
2007-08-07 |
Low power sigma delta modulator with dynamic biasing for audio applications
|
Chen, Hsin-liang; Lee, Yi-sheng; Chiang, Jen-shiun |
| 淡江大學 |
2005-07-01 |
Low power sigma-delta modulator with dynamic biasing for voice band applications
|
Chiang, Jen-shiun; Wu, Chun-cheng; Chen, Hsin-liang; Li, Yi-tsung |
| 臺大學術典藏 |
2018-09-10T08:47:32Z |
Low Power SRAM Cell
|
Feipei Lai; Feipei Lai; FEI-PEI LAI |
| 國立交通大學 |
2014-12-16T06:13:54Z |
Low power static random access memory
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 國立交通大學 |
2014-12-16T06:15:18Z |
LOW POWER STATIC RANDOM ACCESS MEMORY
|
Chuang Ching-Te; Yang Hao-I; Hsia Mao-Chih; Hwang Wei; Chen Chia-Cheng; Shih Wei-Chiang |
| 臺大學術典藏 |
2018-09-10T07:26:44Z |
Low power strategy about correlator array for CDMA baseband processor
|
Ku, Chung-Wei; Kuo, Fu-Yen; Chen, Chi-Kuang; Chen, Liang-Gee; LIANG-GEE CHEN |
| 國立中山大學 |
1997-07 |
Low power technology mapping by hiding high-transition paths in invisible edges for LUT-based FPGAs
|
C.C. Wang;C.P. Kwan |
| 元智大學 |
2016-08-25 |
Low power through body biasing to realize a 3.9-mW CMOS inductorless LNA for LoRa applications
|
Yu-Chu Yang; Jeng-Rern Yang |
| 元智大學 |
2016-08-25 |
Low power through body biasing to realize a 3.9-mW CMOS inductorless LNA for LoRa applications
|
Yu-Chu Yang; Jeng-Rern Yang |
Showing items 557616-557625 of 2348638 (234864 Page(s) Totally)
<< < 55757 55758 55759 55760 55761 55762 55763 55764 55765 55766 > >>
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