English  |  正體中文  |  简体中文  |  0  
???header.visitor??? :  53188577    ???header.onlineuser??? :  1086
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

???jsp.browse.items-by-title.jump??? [ ???jsp.browse.general.jump2chinese??? ] [ ???jsp.browse.general.jump2numbers??? ] [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ]
???jsp.browse.items-by-title.enter???   

Showing items 714426-714450 of 2348943  (93958 Page(s) Totally)
<< < 28573 28574 28575 28576 28577 28578 28579 28580 28581 28582 > >>
View [10|25|50] records per page

Institution Date Title Author
國立聯合大學 2010 Reconfigurable architecture for VLSI 9/7-5/3 wavelet filter Sung, Tze-Yun; Hsin, Hsi-Chin
國立聯合大學 2010 Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter Tze-Yun Sung, Hsi-Chin Hsin
中華大學 2010 Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter 宋志雲; Sung, Tze-Yun
中華大學 2010 Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter 宋志雲; Sung, Tze-Yun
元智大學 2012-11 Reconfigurable Bandpass Filter With Separately Relocatable Passband Edge 蔡炫儒; Nan-Wei Chen; S.-K. Jeng
臺大學術典藏 2018-09-10T09:22:41Z Reconfigurable Bandpass Filter With Separately Relocatable Passband Edge Hsuan-Ju Tsai;Nan-Wei Chen;Shyh-Kang Jeng; Hsuan-Ju Tsai; Nan-Wei Chen; Shyh-Kang Jeng; SHYH-KANG JENG
國立交通大學 2019-04-02T06:00:28Z Reconfigurable Boolean Logic in Memristive Crossbar: The Principle and Implementation Hu, Si-Yu; Li, Yi; Cheng, Long; Wang, Zhuo-Rui; Chang, Ting-Chang; Sze, Simon M.; Miao, Xiang-Shui
國立臺灣大學 2011 Reconfigurable cache memory architecture for integral image and integral histogram applications Hsu, Po-Hao; Chien, Shao-Yi
臺大學術典藏 2018-09-10T08:42:33Z Reconfigurable cache memory architecture for integral image and integral histogram applications Hsu, P.-H.;Chien, S.-Y.; Hsu, P.-H.; Chien, S.-Y.; SHAO-YI CHIEN
元智大學 2019-05-20 Reconfigurable check node unit design of dual-standard LDPC decoding for 60GHz wireless local area network Hsin-Hao Su; Tang-Syun Chen; Cheng-Hung Lin
元智大學 2019/5/20 Reconfigurable check node unit design of dual-standard LDPC decoding for 60GHz wireless local area network Hsin-Hao Su; Tang-Syun Chen; Cheng-Hung Lin
元智大學 2019-05-20 Reconfigurable check node unit design of dual-standard LDPC decoding for 60GHz wireless local area network Hsin-Hao Su; Tang-Syun Chen; Cheng-Hung Lin
國立彰化師範大學 2010-08 Reconfigurable Circularly-Polarized Patch Antenna With Conical Beam Row, Jeen-Sheen; Chan, Ming-Che
臺大學術典藏 2018-09-10T06:38:03Z Reconfigurable color Doppler DSP engine for high-frequency ultrasonic imaging systems T.-H. Yu; S.-Y. Sun; C.-L. Ding; P.-C. Li; A.-Y. (; y) Wu; PAI-CHI LI; AN-YEU(ANDY) WU
臺大學術典藏 2020-04-16T02:35:51Z Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. Yu, Tzu-Hao; Sun, Shih-Yu; Ding, Chih-Liang; Li, Pai-Chi; Wu, An-Yeu; PAI-CHI LI
國立臺灣科技大學 2015 Reconfigurable content-based image retrieval on peer-to-peer networks Su, C.-R.;Chen, J.-J.
亞洲大學 2006-06 Reconfigurable Coordination Model for Dynamic Autonomous Real-Time Systems Jeffrey J. P. Tsai;S.P. Ren and L. Shen
亞洲大學 2006-06 Reconfigurable Coordination Model for Dynamic Autonomous Real-Time Systems 蔡進發;Jeffrey, J.P.Tsai
亞洲大學 2006.06 Reconfigurable Coordination Model for Dynamic Autonomous Real-Time Systems L.Shen;L.Shen;蔡進發;Jeffrey, J.P.Tsai
臺大學術典藏 1986 Reconfigurable Cube-Connected Cycles Architectures Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.; 郭斯彥; Banerjee, P.;郭斯彥;Fuchs, W. K.; Banerjee, P.;Kuo, Sy-Yen;Fuchs, W. K.; Banerjee, P.
國立臺灣大學 1991-01 Reconfigurable Cube-Connected Cycles Architectures 郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.
國立臺灣大學 1986 Reconfigurable Cube-Connected Cycles Architectures Banerjee, P.; 郭斯彥; Fuchs, W. K.; Banerjee, P.; Kuo, Sy-Yen; Fuchs, W. K.
臺大學術典藏 2020-06-11T06:44:37Z Reconfigurable Cube-Connected Cycles Architectures. Kuo, Sy-Yen;Fuchs, W. Kent; Kuo, Sy-Yen; Fuchs, W. Kent; SY-YEN KUO
國立交通大學 2015-12-02T02:59:19Z Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors Wu, I-Wei; Shann, Jean Jyh-Jiun; Chung, Chung-Ping
國立交通大學 2014-12-08T15:02:18Z Reconfigurable depth buffer compression design for 3D graphics system Jung, Tzung-Rung; Van, Lan-Da; Fang, Wai-Chi; Shen, Teng-Yao

Showing items 714426-714450 of 2348943  (93958 Page(s) Totally)
<< < 28573 28574 28575 28576 28577 28578 28579 28580 28581 28582 > >>
View [10|25|50] records per page