臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T06:32:26Z	VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps	RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG
臺大學術典藏	2018-09-10T08:34:15Z	VLSI design and implementation of density-based spike classification for neuroprosthetic applications	Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立聯合大學	2004	VLSI Design and Implementation of The Re-configurable 2-D Von Neumann Cellular Automata Bases Generator for The Image Processing Applications	陳榮堅, 賴瑞麟
國立交通大學	2014-12-08T15:46:11Z	VLSI design for high-speed LZ-based data compression	Chen, JM; Wei, CH
國立中山大學	1998-06	VLSI design of A 1.0 GHz 0.6-µm 8-Bit CLA using PLA-styled all-N-transistor Logic	C.C. Wang;K.C. Tsai
國立交通大學	2014-12-08T15:27:27Z	VLSI design of a priority arbitrator for shared buffer ATM switches	Lin, YS; Yang, SC; Fang, SJ; Shung, CB
臺大學術典藏	2018-09-10T04:13:19Z	VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems	Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
國立臺灣大學	2002-08	VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems	Hsu, Huai-Yi; Wu, An-Yeu
臺大學術典藏	2003	VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems	Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu; Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu
臺大學術典藏	2019-10-24T07:57:17Z	VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems	吳安宇;AN-YEU(ANDY) WU;An-Yeu Wu;Chih-Hsiu Lin;Ching-Hua Wen;Jen-Chih Kuo; Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu; AN-YEU(ANDY) WU; 吳安宇

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