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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 91721-91730 / 2348570 (共234857页)
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| 國立交通大學 |
2017-04-21T06:49:42Z |
A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
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Hong, Zheng-Hao; Chen, Wei-Zen |
| 國立交通大學 |
2016-03-28T00:04:12Z |
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
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Hong, Zheng-Hao; Liu, Yao-Chia; Chen, Wei-Zen |
| 國立交通大學 |
2014-12-08T15:09:08Z |
A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer
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Chen, Wei-Zen; Huang, Shih-Hao; Wu, Guo-Wei; Liu, Chuan-Chang; Huang, Yang-Tung; Chiu, Chin-Fong; Chang, Wen-Hsu; Juang, Ying-Zong |
| 國立臺灣大學 |
2004 |
A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet
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Yang, Rong-Jyi; Chen, Shang-Ping; Liu, Shen-Iuan |
| 國立交通大學 |
2017-04-21T06:49:35Z |
A 3.2 mW MIXED-SIGNAL READOUT CIRCUIT FOR AN ORGANIC VERTICAL NANO-JUNCTIONS SENSOR
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Chao, Paul C. -P.; Su, Chin-I; Tran, Trong-Hieu; Zan, Hsiao-Wen |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
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Tai, H.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立臺灣大學 |
2008 |
A 3.3 mW K-Band 0.18μm 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair
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Huang, Kuo-Ken; Chiang, Meng-Ju; Tzuang, C.-K.C. |
| 淡江大學 |
1998-05-31 |
A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock
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江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan |
| 淡江大學 |
1998-11-24 |
A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique
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江正雄; Chiang, Jen-shiun; Chou, Pao-chu |
| 國立臺灣大學 |
1998 |
A 3.3-V CMOS Wideband Exponential Control Variable-Gain-Amplifier
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Huang, Po-Chiun; Li-Yu Chiou; 汪重光; Huang, Po-Chiun; Li-Yu Chiou; Wang, Chorng-Kuang |
显示项目 91721-91730 / 2348570 (共234857页)
<< < 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 > >>
每页显示[10|25|50]项目
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