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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:24:55Z	Low-Power and High-Throughput Design of Fast Motion Estimation VLSI Architecture for Multimedia System-on-Chip Design	Sy-Yen Kuo;Shih-Chia Huang; Sy-Yen Kuo; Shih-Chia Huang; SY-YEN KUO
國立交通大學	2014-12-08T15:28:51Z	Low-Power and Highly Reliable Multilevel Operation in ZrO(2) 1T1R RRAM	Wu, Ming-Chi; Lin, Yi-Wei; Jang, Wen-Yueh; Lin, Chen-Hsi; Tseng, Tseung-Yuen
國立交通大學	2019-04-02T05:58:57Z	Low-Power and Highly Reliable Multilevel Operation in ZrO2 1T1R RRAM	Wu, Ming-Chi; Lin, Yi-Wei; Jang, Wen-Yueh; Lin, Chen-Hsi; Tseng, Tseung-Yuen
臺大學術典藏	2018-09-10T04:56:07Z	Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion	Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU
國立成功大學	2019-05	Low-Power and Low-Phase-Noise G(m)-Enhanced Current-Reuse Differential Colpitts VCO	Cheng;Kuang-Wei;Chang;Sheng-Kai;Huang;Yu-Chieh
國立成功大學	2019	Low-Power and Low-Phase-Noise Gm-Enhanced Current-Reuse Differential Colpitts VCO	Cheng, K.-W.;Chang, S.-K.;Huang, Y.-C.
中華大學	2006	Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT	宋志雲; Sung, Tze-Yun
中華大學	2006	Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT	謝曜式; Shieh, Yaw-Shih
國立交通大學	2019-04-02T06:04:41Z	Low-power and Reference-Less data and clock recovery circuit for visible light receivers	Liu, Ming-Cheng; Chao, Paul C. -P.; Khiong, Soh Sze
國立成功大學	2009-12	Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application	Lin, Jin-Fu; Chang, Soon-Jyh; Chiu, Chin-Fong; Tsai, Hann-Huei; Wang, Jiann-Jong

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