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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 558771-558780 / 2348570 (共234857页)
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每页显示[10|25|50]项目
| 臺大學術典藏 |
2018-09-10T09:24:55Z |
Low-Power and High-Throughput Design of Fast Motion Estimation VLSI Architecture for Multimedia System-on-Chip Design
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Sy-Yen Kuo;Shih-Chia Huang; Sy-Yen Kuo; Shih-Chia Huang; SY-YEN KUO |
| 國立交通大學 |
2014-12-08T15:28:51Z |
Low-Power and Highly Reliable Multilevel Operation in ZrO(2) 1T1R RRAM
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Wu, Ming-Chi; Lin, Yi-Wei; Jang, Wen-Yueh; Lin, Chen-Hsi; Tseng, Tseung-Yuen |
| 國立交通大學 |
2019-04-02T05:58:57Z |
Low-Power and Highly Reliable Multilevel Operation in ZrO2 1T1R RRAM
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Wu, Ming-Chi; Lin, Yi-Wei; Jang, Wen-Yueh; Lin, Chen-Hsi; Tseng, Tseung-Yuen |
| 臺大學術典藏 |
2018-09-10T04:56:07Z |
Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion
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Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU |
| 國立成功大學 |
2019-05 |
Low-Power and Low-Phase-Noise G(m)-Enhanced Current-Reuse Differential Colpitts VCO
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Cheng;Kuang-Wei;Chang;Sheng-Kai;Huang;Yu-Chieh |
| 國立成功大學 |
2019 |
Low-Power and Low-Phase-Noise Gm-Enhanced Current-Reuse Differential Colpitts VCO
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Cheng, K.-W.;Chang, S.-K.;Huang, Y.-C. |
| 中華大學 |
2006 |
Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT
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宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Low-Power and Multiplierless Architectures for Line-Based 2-D DWT and IDWT
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謝曜式; Shieh, Yaw-Shih |
| 國立交通大學 |
2019-04-02T06:04:41Z |
Low-power and Reference-Less data and clock recovery circuit for visible light receivers
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Liu, Ming-Cheng; Chao, Paul C. -P.; Khiong, Soh Sze |
| 國立成功大學 |
2009-12 |
Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application
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Lin, Jin-Fu; Chang, Soon-Jyh; Chiu, Chin-Fong; Tsai, Hann-Huei; Wang, Jiann-Jong |
显示项目 558771-558780 / 2348570 (共234857页)
<< < 55873 55874 55875 55876 55877 55878 55879 55880 55881 55882 > >>
每页显示[10|25|50]项目
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