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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 310886-310895 / 2348973 (共234898页)
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| 國立成功大學 |
2023-11 |
Design and Analysis of Consequent-Pole Permanent Magnet Vernier Motor With Cancellation of Even-Order Harmonics
|
Hsieh;Min-Fu;Chang;Chia-Yuan;Huynh;Thanh-Anh;Dorrell;D, G. |
| 國立交通大學 |
2014-12-08T15:11:08Z |
Design and analysis of contention-based request schemes for best-effort traffics in IEEE 802.16 networks
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Chen, Lien-Wu; Tseng, Yu-Chee |
| 朝陽科技大學 |
2020-02 |
Design and Analysis of Coupled-Inductor Switched-Capacitor Boost DC-AC Inverter
|
張原豪;廖俊嘉 |
| 臺大學術典藏 |
2018-09-10T04:55:24Z |
Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode
|
Ren-Chieh Liu; Chin-Shen Lin; Kuo-Liang Deng; Huei Wang; HUEI WANG |
| 國立臺灣大學 |
2004 |
Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode distributed amplifiers
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Liu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, Huei |
| 國立交通大學 |
2018-08-21T05:56:38Z |
Design and Analysis of Deadline and Budget Constrained Autoscaling (DBCA) Algorithm for 5G Mobile Networks
|
Than Phung-Duc; Ren, Yi; Chen, Jyh-Cheng; Yu, Zheng-Wei |
| 臺大學術典藏 |
1992-01 |
Design and analysis of defect tolerant hierarchical sorting networks
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Kuo, Sy-Yen; Liang, Sheng-Chiech; Kuo, Sy-Yen; Liang, Sheng-Chiech |
| 國立臺灣大學 |
1992-01 |
Design and analysis of defect tolerant hierarchical sorting networks
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Kuo, Sy-Yen; Liang, Sheng-Chiech |
| 國立臺灣大學 |
1989 |
Design and Analysis of Defect Tolerant Hierarchical Sorting Networks
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郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C. |
| 臺大學術典藏 |
2020-06-11T06:44:46Z |
Design and Analysis of Defect Tolerant Hierarchical Sorting Networks
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Kuo, S.-Y.;Liang, S.-C.; Kuo, S.-Y.; Liang, S.-C.; SY-YEN KUO |
显示项目 310886-310895 / 2348973 (共234898页)
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每页显示[10|25|50]项目
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