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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 315186-315195 / 2348973 (共234898页)
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| 亞洲大學 |
2011.12 |
Design of Power Virtual Harmonic Based On IEC Std. 61000-4-7 Analyzer
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陳正一;Chen, Cheng-I |
| 臺大學術典藏 |
2018-09-10T08:10:54Z |
Design of power-assisted motor for vehicle air-conditioning systems
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Yang, Y.-P.; Liu, H.-F.; Liu, J.-J.; YEE-PIEN YANG |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design of power-aware multiplier with graceful quality-power trade-offs
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Yen, JH; Dung, LR; Shen, CY |
| 國立中山大學 |
2009-04 |
Design of Power-Efficient Configurable Booth Multiplier
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Shiann-Rong Kung;Jiun-Ping Wang |
| 國立中山大學 |
2007 |
Design of power-efficient pipelined truncated multipliers with various output precision
|
S.R. Kuang;J.P. Wang |
| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:50Z |
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
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Wang, Chang-Tzu; Ker, Ming-Dou |
| 義守大學 |
2009-03 |
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
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Chang-Tzu Wang;Ming-Dou Ker |
| 國立交通大學 |
2018-08-21T05:53:21Z |
Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events
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Chen, Jie-Ting; Ker, Ming-Dou |
| 國立臺灣科技大學 |
2018 |
Design of PPC Buffer for Diff-RAID/PPC
|
林紘立 |
显示项目 315186-315195 / 2348973 (共234898页)
<< < 31514 31515 31516 31517 31518 31519 31520 31521 31522 31523 > >>
每页显示[10|25|50]项目
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