| 臺大學術典藏 |
2018-09-10T07:41:47Z |
"Gated Scheduling Algorithms in Packet Switching ","Networks"
|
ZSEHONG TSAI; F.-M.Tsou; Z. Tsai |
| 國立交通大學 |
2019-04-03T06:43:59Z |
Gate tunable spin-orbit coupling and weak antilocalization effect in an epitaxial La2/3Sr1/3MnO3 thin film
|
Chiu, Shao-Pin; Yamanouchi, Michihiko; Oyamada, Tatsuro; Ohta, Hiromichi; Lin, Juhn-Jong |
| 臺大學術典藏 |
2018-09-10T08:18:06Z |
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect
|
H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T07:41:37Z |
Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect
|
H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO |
| 國立高雄師範大學 |
2010 |
Gate voltage swing enhancement of an InGaP/InGaAs pseudomorphic HFET with low-to-high double doping channels
|
Jung-Hui Tsai;Wen-Shiung Lour;Chia-Hua Huang;Sheng-Shiun Ye;Yung-Chun Ma; 蔡榮輝 |
| 國立臺灣海洋大學 |
2010-10-28 |
Gate voltage swing enhancement of InGaP/ InGaAs pseudomorphic HFET with low-to-high double doping channels
|
J.-H. Tsai; W.-S. Lour; C.-H. Huang; S.-S. Ye; Y.-C. Ma |
| 臺大學術典藏 |
2018-09-10T07:04:10Z |
Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor
|
Liao, M.H.; Liu, C.W.; Yeh, L.; Lee, T.-L.; Liang, M.-S.; CHEE-WEE LIU |
| 臺大學術典藏 |
2020-01-13T08:22:40Z |
Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor
|
Liao, M.H.; Liu, C.W.; Yeh, L.; Lee, T.-L.; Liang, M.-S.; MING-HAN LIAO |
| 國立交通大學 |
2014-12-08T15:36:25Z |
Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels
|
Tsai, Jung-Ruey; Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan |
| 臺大學術典藏 |
2018-09-10T14:58:05Z |
Gate-all-around Ge FETs
|
Liu, C.W.;Chen, Y.-T.;Hsu, S.-H.; Liu, C.W.; Chen, Y.-T.; Hsu, S.-H.; CHEE-WEE LIU |
| 國立交通大學 |
2014-12-08T15:11:50Z |
Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
|
Su, Chun-Jung; Tsai, Tzu-I; Liou, Yu-Ling; Lin, Zer-Ming; Lin, Horng-Chih; Chao, Tien-Sheng |
| 國立交通大學 |
2015-12-02T02:59:20Z |
Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels
|
Tso, Chia-Tsung; Liu, Tung-Yu; Sheu, Jeng-Tzong |
| 國立交通大學 |
2014-12-08T15:27:28Z |
Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels
|
Kang, Tsung-Kuei; Liao, Ta-Chuan; Lin, Chia-Min; Liu, Han-Wen; Wang, Fang-Hsing; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:22:22Z |
Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels
|
Liao, Ta-Chuan; Kang, Tsung-Kuei; Lin, Chia-Min; Wu, Chun-Yu; Cheng, Huang-Chung |
| 國立交通大學 |
2014-12-08T15:30:22Z |
Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope
|
Liu, Tung-Yu; Lo, Shen-Chuan; Sheu, Jeng-Tzong |
| 國立成功大學 |
2004-11-22 |
Gate-alloy-related kink effect for metamorphic high-electron-mobility transistors
|
Chen, Y. J.; Hsu, Wei-Chou; Lee, C. S.; Wang, T. B.; Tseng, C. H.; Huang, J. C.; Huang, D. H.; Wu, C. L. |
| 臺大學術典藏 |
2018-09-10T14:57:38Z |
Gate-bias stress stability of P-type SnO thin-film transistors fabricated by RF-sputtering
|
Chiu, I.-C.;Cheng, I.-C.; Chiu, I.-C.; Cheng, I.-C.; I-CHUN CHENG |
| 國立交通大學 |
2015-12-04T07:03:11Z |
GATE-BOOSTING RECTIFIER AND METHOD OF PERMITTING CURRENT TO FLOW IN FAVOR OF ONE DIRECTION WHEN DRIVEN BY AC INPUT VOLTAGE
|
Wang Yu-Jiu; Liao I-No; Tsai Chao-Han; Pakasiri Chatrpol |
| 國立中山大學 |
2006 |
Gate-controlled spin splitting in GaN/AlN quantum wells
|
Ikai Lo;W.T. Wang;M.H. Gao;J.K. Tsai;S.F. Tsay;J.C. Chiang |
| 國立中山大學 |
2006 |
Gate-controlled Spin Splitting in GaN/AlN Quantum Wells
|
Ikai Lo;W.T. Wang;M.H. Gau;S.F. Tsay;Jih-Chen Chiang |
| 國立中山大學 |
2006 |
Gate-Controlled Spin Splitting in GaN/AlN Quantum Wells
|
Ikai Lo;W.T. Wang;M.H. Gau;J.K. Tsai;S.F. Tsay;J.C. Chiang |
| 國立交通大學 |
2014-12-08T15:17:41Z |
Gate-controlled ZnO nanowires for field-emission device application
|
Li, SY; Lee, CY; Lin, P; Tseng, TY |
| 國立交通大學 |
2014-12-08T15:31:00Z |
Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack
|
Cheng, C. H.; Chou, K. I.; Chin, A. |
| 國立交通大學 |
2014-12-08T15:47:59Z |
Gate-First TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs Using Laser Annealing
|
Chen, W. B.; Wu, C. H.; Shie, B. S.; Chin, Albert |
| 中華大學 |
2010 |
Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
|
吳建宏; rossiwu |
| 國立交通大學 |
2019-04-02T06:00:27Z |
Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
|
Chen, W. B.; Wu, C. H.; Shie, B. S.; Chin, Albert |
| 國立交通大學 |
2019-04-02T05:58:20Z |
Gate-induced localized states in graphene: Topological nature in their formation
|
Wang, L. Y.; Chang, Che-Yuan; Chu, C. S. |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
|
B. Chung; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:16Z |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
|
B. Chung; J. B. Kuo; JAMES-B KUO |
| 國立臺灣大學 |
2008 |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application
|
Chung, B.; Kuo, J.B. |
| 臺大學術典藏 |
2018-09-10T07:08:18Z |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application
|
JAMES-B KUO; B. Chung; J. B. Kuo |
| 臺大學術典藏 |
2018-09-10T07:08:19Z |
Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications
|
R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO |
| 國立臺灣海洋大學 |
2006 |
Gate-metal formation-related kink effect and gate current on In0.5Al0.5As/In0.5Ga0.5As metamorphic high electron mobility transistor performance
|
M. K. Hsu;H. R. Chen;S. Y. Chiou;W. T. Chen;G. H. Chen;Y. C. Chang;W. S. Lour |
| 國立臺灣海洋大學 |
2017 |
Gate-opening upon CO2 adsorption on a metal–organic framework that mimics a natural stimuli-response system.
|
T. W. Tseng;L. W. Lee;T. T. Luo;P. H. Chien;Y. H. Liu;S. L. Lee;C. M. Wang;K. L. Lu |
| 國立交通大學 |
2014-12-08T15:24:59Z |
Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立成功大學 |
2016-03-15 |
Gate-Recessed AlGaN/GaN ISFET Urea Biosensor Fabricated by Photoelectrochemical Method
|
Lee, Ching-Ting; Chiu, Ying-Shuo |
| 國立交通大學 |
2017-04-21T06:49:45Z |
Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices
|
Lai, Wei-Ting; Yang, Kuo-Ching; Liao, Po-Hsiang; George, Thomas; Li, Pei-Wen |
| 國立交通大學 |
2019-04-03T06:36:44Z |
Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors
|
Lai, Wei-Ting; Yang, Kuo-Ching; Liao, Po-Hsiang; George, Tom; Li, Pei-Wen |
| 國立交通大學 |
2014-12-08T15:08:03Z |
Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress
|
Hsieh, Zhen-Ying; Wang, Mu-Chun; Chen, Shuang-Yuan; Chen, Chih; Huang, Heng-Sheng |
| 國立成功大學 |
2015-07-06 |
Gate-tunable coherent transport in Se-capped Bi2Se3 grown on amorphous SiO2/Si
|
Liu, Y. H.; Chong, C. W.; Jheng, J. L.; Huang, S. Y.; Huang, J. C. A.; Li, Z.; Qiu, H.; Huang, S. M.; Marchenkov, V. V. |
| 國立成功大學 |
2019 |
Gate-Tunable Fano Resonances in Parallel-Polyacene-Bridged Carbon Nanotubes
|
Dou, K.P.;Chang, Chang C.-H.;Kaun, C.-C. |
| 國立成功大學 |
2019-02-21 |
Gate-Tunable Fano Resonances in Parallel-Polyacene-Bridged Carbon Nanotubes
|
張景皓; Chang, Ching-Hao; Dou, Kun Peng;Kaun, Chao-Cheng |
| 國立政治大學 |
2014-05 |
Gate-tunable Kondo resistivity and dephasing rate in graphene studied by numerical renormalization group calculations
|
Lo, Po-Wei;Guo, Guang-Yu;Anders, Frithjof B.; 郭光宇 |
| 國立成功大學 |
2020-11-11 |
Gate-Tunable Two-Dimensional Superlattices in Graphene
|
Huber;Robin;Liu;Ming-Hao;Chen;Szu-Chao;Drienovsky;Martin;Sandner;Andreas;Watanabe;Kenji;Taniguchi;Takashi;Richter;Klaus;Weiss;Dieter;Eroms;Jonathan |
| 國立成功大學 |
2012-10-22 |
Gate-voltage-dependent Landau levels in AA-stacked bilayer graphene
|
Tsai, Sing-Jyun; Chiu, Yu-Huang; Ho, Yen-Hung; Lin, Ming-Fa |
| 國立成功大學 |
2008-10-16 |
Gateaux differentiability of the dual gap function of a variational inequality
|
Wu, Zili; Wu, Soon-Yi |
| 國立成功大學 |
2020 |
Gated Recurrent Unit Network-based Cellular Trafile Prediction
|
Lens, Shiang E.P.;Chien, W.-C.;Lai, C.-F.;Chao, H.-C. |
| 國立成功大學 |
2023-06 |
Gated Recurrent Units and Recurrent Neural Network Based Multimodal Approach for Automatic Video Summarization
|
Kaur;Lakhwinder;Aljrees;Turki;Kumar;Ankit;Pandey;Kumar, Saroj;Singh;Udham, Kamred;Mishra;Kumar, Pankaj;Singh;Teekam |
| 國立臺灣大學 |
1999-10 |
Gated-scheduling algorithms in packet switching networks
|
Tsou, Fu-Ming; Tsai, Zsehong |
| 臺大學術典藏 |
2018-09-10T09:51:41Z |
Gatekeeper or Facilitator: General Counsel and Corporate Tax Avoidance.
|
Shu-Ling Wu; Shu-Ling Wu; SHU-LING WU |
