| 國立高雄師範大學 |
2009-11 |
Design of Zero Reference Codes Using Cross-Entropy Method
|
陳榮杰; Jung-Chieh Chen |
| 國立成功大學 |
2006-06-15 |
Design of ZnO/Ag/ZnO multilayer transparent conductive films
|
Sahu, Diptiranjan; Huang, Jow-Lay |
| 臺大學術典藏 |
2010 |
Design of zone configuration scheme for wireless zone-based multicast and broadcast service
|
Hu, K.-H.;Fu, H.-L.;Lin, P.; Hu, K.-H.; Fu, H.-L.; Lin, P.; PHONE LIN |
| 臺大學術典藏 |
2010 |
Design of zone configuration scheme for wireless zone-based multicast and broadcast service.
|
Fu, Huai-Lei; Hu, Kai-Hsiang; Hu, Kai-Hsiang;Fu, Huai-Lei;Lin, Phone; Lin, Phone; PHONE LIN |
| 國立暨南國際大學 |
2011 |
Design of zone-based bandwidth management scheme in IEEE 802.16 multi-hop relay networks
|
Chen, KY; Chen, KY |
| 國立交通大學 |
2014-12-08T15:26:51Z |
Design on ESD protection circuit with very low and constant input capacitance
|
Chen, TY; Ker, MD |
| 國立交通大學 |
2014-12-08T15:38:45Z |
Design on ESD protection scheme for IC with power-down-mode operation
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2019-04-02T06:04:44Z |
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications
|
Ker, Ming-Dou; Wu, Chien-Hua |
| 義守大學 |
2015-06 |
Design on MEMS-based 3D biochip for drug-released dispenser
|
Hsiang-Chen Hsu;Li-Ming Chu;Baojun Liu;Chien-Yuan Lai |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications
|
Ker, MD; Chen, SL; Tsai, CS |
| 國立交通大學 |
2014-12-08T15:16:38Z |
Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability
|
Ker, Ming-Dou; Hu, Fang-Ling |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
|
Chen, Zi-Ping; Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, Ming-Dou; Chen, Wen-Yi; Hsu, Kuo-Chun |
| 國立交通大學 |
2014-12-08T15:25:22Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, MD; Chen, WY; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:43:10Z |
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
|
Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:45:27Z |
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
|
Ker, MD; Lo, WY |
| 國立屏東大學 |
2011 |
Design optimal control of ship maneuver patterns for conllision avoidance : a review
|
陳震遠;C.H.Shih;Huang, Po-Hsuan;Yamamura, Saburo |
| 淡江大學 |
2009-10 |
Design Optimization and Analysis Applying DOE for Intake and Exhaust Pipeline of a Motorcycle
|
史建中 |
| 義守大學 |
2016-01 |
Design Optimization and Implementation of Genetic-Based Moving Sliding Manifold Strategy for Parallel Operation of DC-AC Converters
|
En-Chih Chang;Hairong Wang;Kuo-Yuan Liao;Rong-Ching Wu |
| 國立臺灣科技大學 |
2017 |
Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly
|
Fang, S.-Y;Hong, Y.-X. |
| 國立臺灣科技大學 |
2017 |
Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly
|
Lin, K.-L.;Fang, S.-Y.;Hong, Y.-X. |
| 臺大學術典藏 |
2021-09-14T23:19:16Z |
Design optimization for ADMM-Based SVM Training Processor for Edge Computing
|
Huang, Shuo An; Hsieh, Yi Yen; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2022-04-25T06:41:37Z |
Design optimization for ADMM-Based SVM Training Processor for Edge Computing
|
Huang S.-A;Hsieh Y.-Y;Yang C.-H.; Huang S.-A; Hsieh Y.-Y; Yang C.-H.; CHIA-HSIANG YANG |
| 臺大學術典藏 |
2000 |
Design optimization for an LPG automobile engine
|
Jaw, Shenq-Yuh; Wu, Tzann-Dwo;Chen, Yih-Nan;Yen, Jia-Yush;Jaw, Shenq-Yuh; Wu, Tzann-Dwo; Chen, Yih-Nan; Yen, Jia-Yush |
| 國立臺灣大學 |
2000 |
Design optimization for an LPG automobile engine
|
Wu, Tzann-Dwo; Chen, Yih-Nan; Yen, Jia-Yush; Jaw, Shenq-Yuh |
