| 臺大學術典藏 |
2004-07-31 |
Area, Delay, Power, and Noise Optimization for Transmission Lines
|
張耀文; 張耀文 |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs for 2-D Inverse Discrete Wavelet Transform Architectures Using Direct Form
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs for 2-D Inverse Discrete Wavelet Transform Architectures Using Direct Form
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs for 2-D Inverse Discrete Wavelet Transform Architectures Using Direct Form
|
林國珍; Lin, Kuo-Jen |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs in the Design of Pipelined 2-D Discrete Wavelet Transform Architectures Using Direct Cascading Form
|
林國珍; Lin, Kuo-Jen |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs in the Design of Pipelined 2-D Discrete Wavelet Transform Architectures Using Direct Cascading Form
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2005 |
Area, Power and Throughput Trade-Offs in the Design of Pipelined 2-D Discrete Wavelet Transform Architectures Using Direct Cascading Form
|
謝曜式; Shieh, Yaw-Shih |
| 國立臺灣科技大學 |
2014 |
Area- and power-efficient DC-DC converter with on-chip compensation
|
Liu, P.-J.;Chang, Y.-H. |
| 元智大學 |
Sep-16 |
Area-aware Decomposition for Single-Electron Transistor Arrays
|
陳勇志; Ching-Hsuan Ho; Chun-Yao Wang; Ching-Yi Huang; Suma Datta; Vijaykrishnan Narayanan |
| 中國文化大學 |
2016-07 |
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach
|
Lee, CY (Lee, Chiou-Yng); Meher, PK (Meher, Pramod Kumar); Liu, CH (Liu, Chung-Hsin) |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation Based on Space Sensitivity Analysis for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2007 |
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity
|
顏金泰; YAN, JIN-TAI |
| 中華大學 |
2006 |
Area-Driven White Space Distribution for Detailed Floorplan Design
|
顏金泰; YAN, JIN-TAI |
| 國立交通大學 |
2014-12-08T15:26:16Z |
Area-effective FIR filter design for multiplier-less implementation
|
Lin, TJ; Yang, TH; Jen, CW |
| 國立交通大學 |
2014-12-16T06:13:48Z |
Area-efficiency delta modulator for quantizing an analog signal
|
Wu Chun-Yu; Lyu Yuan-Fu |
| 國立臺灣海洋大學 |
2014 |
Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems
|
Chu Yu;Mao-Hsu Yen |
| 國立交通大學 |
2015-07-21T08:30:52Z |
Area-Efficient 2-D Digital Filter Architectures Possessing Diagonal and Four-Fold Rotational Symmetries
|
Chen, Pei-Yu; Van, Lan-Da; Reddy, Hari C.; Khoo, I-Hung |
| 國立交通大學 |
2016-03-28T00:04:24Z |
Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection
|
Lin, Chun-Yu; Wu, Po-Han; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:04:34Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立交通大學 |
2014-12-08T15:04:32Z |
AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
|
SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK |
| 國立中山大學 |
2001-09 |
Area-Efficient Carry-Save Full Adder Design Using Pass Transistors
|
Tso-Bing Juan; Ming-Ju Tsia; Shen-Fu Hsiao |
| 國立交通大學 |
2015-12-02T02:59:12Z |
Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:34Z |
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 義守大學 |
2009-05 |
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
|
Shih-Hung Chen;Ming-Dou Ker |
| 國立彰化師範大學 |
2010-08 |
Area-Efficient High Goodness-of-Fit Noise Generator for Communication Test
|
Chen, Pin-Chung; Fan, Sheng-Jie; Wang, Yun-Ping; Kao, Yung-Sheng; Huang, Tsung-Chu |
