| 國立交通大學 |
2014-12-08T15:27:06Z |
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration
|
Wu, I-Wei; Chung, Chung-Ping; Shann, Jean Jyh-Jiun |
| 國立交通大學 |
2019-08-02T02:18:28Z |
Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction
|
Chen, Wen-Chieh; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:47Z |
Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 臺大學術典藏 |
2011 |
Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding
|
Lin, C.-H.;Chen, C.-Y.;Wu, A.-Y.; Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 臺大學術典藏 |
2019-10-24T07:57:12Z |
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu Wu;Chun-Yu Chen;Chen-Hung Lin; Chen-Hung Lin; Chun-Yu Chen; An-Yeu Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 國立交通大學 |
2015-07-21T08:31:30Z |
Area-efficient TFM-based Stochastic Decoder Design for Non-binary LDPC Codes
|
Yang, Chih-Wen; Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立彰化師範大學 |
2008-07 |
Area-Efficient True One-Period Delay Jitter Measurement
|
Yang, Cheng-Han; Chou, Yi-Hsian; Huang, Tsung-Chu |
| 國立彰化師範大學 |
2008-08 |
Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement
|
Yang, Cheng-Han; Chou, Yi-Hsian; Huang, Tsung-Chu |
| 國立成功大學 |
2023 |
Area-Efficient VLSI Architecture of Key Switching for BGV Fully Homomorphic Encryption
|
Chen, K.-Y.;Shieh, M.-D. |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems
|
Hsu, Huai-Yi; Wu, An-Yeu (Andy); Yeo, Jih-Chiang |
| 臺大學術典藏 |
2019-10-24T07:57:16Z |
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems
|
吳安宇;AN-YEU(ANDY) WU;Jih-Chiang Yeo;An-Yeu Wu;Huai-Yi Hsu; Huai-Yi Hsu; An-Yeu Wu; Jih-Chiang Yeo; AN-YEU(ANDY) WU; 吳安宇 |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Area-I/O flip-chip routing for chip-package co-design
|
Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 國立臺灣大學 |
2010 |
Area-I/O flip-chip routing for chip-package co-design considering signal skews
|
Fang, J.-W.; Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Area-I/O flip-chip routing for chip-package co-design considering signal skews
|
Fang, J.-W.; Chang, Y.-W.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 國立交通大學 |
2018-08-21T05:56:51Z |
Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment
|
Lin, Kun-Sheng; Hsu, Hsin-Wu; Lee, Ren-Jie; Chen, Hung-Ming |
| 國立中山大學 |
2008-05 |
Area-Oriented Pass-Transistor Logic Synthesis Using Buffer Elimination and Layout Compaction
|
Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen |
| 國立臺灣科技大學 |
2017 |
Area-partitioned clustering and cluster head rotation for wireless sensor networks
|
Ferng, H.-W.;Chuang, J.-S. |
| 國立臺灣大學 |
1985 |
Area-period tradeoffs for multiplication of rectangular matrices
|
Lin, Ferng-Ching; Wu, I-Chen |
| 臺大學術典藏 |
2022-04-25T06:12:45Z |
Area-population control of fungus-growing termite, Odontotermes formosanus, using hexaflumuron durable baits
|
Chiu C.-I;Chuang Y.-H;Liang W.-R;Yeh H.-T;Yang H.-Y;Tsai M.-J;Spomer N.A;Li H.-F.; Chiu C.-I; Chuang Y.-H; Liang W.-R; Yeh H.-T; Yang H.-Y; Tsai M.-J; Spomer N.A; Li H.-F.; MING-JER TSAI |
| 國立交通大學 |
2018-08-21T05:56:48Z |
Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Application
|
Chen, Jr-Ming; Huang, Po-Tsang; Wu, Shang-Lin; Hwang, Wei; Chuang, Ching-Te |
| 國立交通大學 |
2018-01-24T07:38:38Z |
Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Applications
|
陳志明; 黃威; 莊景德; Chen, Jr-Ming |
| 國立交通大學 |
2014-12-08T15:35:47Z |
Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications
|
Huang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:27:53Z |
AREA-RATIO-CONSTRAINED MIN-CUT PARTITIONING FOR ROW-BASED PLACEMENT
|
YAN, JT |
