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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
國立臺灣大學 1992-11 Test set compaction for combinational circuits Chang, Jau-Shien; Lin, Chen-Shang
國立臺灣大學 1992-11 Test Set Compaction for Combinational Circuits Chang, J.; 林呈祥; Chang, J.; Lin, Chen-Shang
淡江大學 2008-11-19 Test Slice Difference Technique for Low Power Testing 饒建奇
淡江大學 2012-06 Test Slice Difference Technique for Low-Transition Test Data Compression 饒建奇; 吳柏翰; 李威霖
淡江大學 2012-06 Test Slice Difference Technique for Low-Transition Test Data Compression Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin
國立成功大學 2017-01 Test Stimulus Compression Based on Broadcast Scan With One Single Input Chen;Jhen-Zong;Lee;Kuen-Jong
國立交通大學 2014-12-08T15:26:13Z Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's Ker, MD; Peng, JJ; Jiang, HC
國立交通大學 2014-12-08T15:09:20Z Test structure on SCR device in waffle layout for RE ESD protection Ker, Ming-Dou; Lin, Chun-Yu
國立交通大學 2014-12-08T15:25:49Z Test structures to verify ESD robustness of on-glass devices in UPS technology Ker, MD; Deng, CK; Yang, SC; Tasi, YM
國立臺灣科技大學 1997 Test Taiwan's High Home Ownership Rates in the 1980's Wu, Couchen;Hsiu-Li Chen
臺大學術典藏 2019-12-10T03:24:45Z test test test CHIEN-JU CHIANG
臺北醫學大學 2007 Test the different surrounding situation of post by resonance frequency. 黃豪銘; Chang KZ; Lin CT; Chang WJ; Huang HM
淡江大學 1995-01-01 Test time reduction for scan-designed circuits by sliding compatibility 張昭憲; Chang, Jau-shien; Lin, Chen-shang
淡江大學 1994-11-16 Test time reduction for scan-designed circuits by sliding compatibility 張昭憲; Chang, Jau-shien; 林呈祥; Lin, Chen-shang
國立臺灣大學 1994-11 Test time reduction for scan-designed circuits by sliding compatibility Chang, Jau-Shien; Lin, Chen-Shang
國立臺灣大學 1995-01 Test time reduction for scan-designed circuits by sliding compatibility Chang, J.-S.; Lin, C.-S.
國立臺灣大學 1994 Test Time Reduction for Scan-Designed Circuits by Sliding Compatibility Chang, J. S.; 林呈祥; Chang, J. S.; Lin, Chen-Shang
國立臺灣大學 1993-02 Test time reduction in scan designed circuits Lai, Wen-Joung; Kung, Chen-Pin; Lin, Chen-Shang
國立臺灣大學 1993 Test Time Reduction in Scan Designed Circuits Lai, W.; Kung, C.; 林呈祥; Lai, W.; Kung, C.; Lin, Chen-Shang
東海大學 2003 Test Web applications based on Agent Xu, L., Xu, B.-W., Chen, H.-W., Chu, W., Lin, J.-M., Yang, H.-J.
臺大學術典藏 2021-05-20T01:39:35Z Test, trace, and isolate in the UK Cheng H.-Y.;Cohen T.;Hsien-Ho Lin; Cheng H.-Y.; Cohen T.; HSIEN-HO LIN
臺大學術典藏 2022-04-20T08:55:01Z Test, trace, and isolate in the UK Cheng H.-Y.; Cohen T.; HSIEN-HO LIN
臺大學術典藏 2018-09-10T08:47:24Z Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI
國立臺灣海洋大學 2018 Test-Oriented RESTful Service Discovery with Semantic Interface Compatibility Shang-Pin Ma;Ying-Jen Chen;Yang Syu;Hsuan-Ju Lin;Yong-Yi FanJiang
臺大學術典藏 2020-04-08T07:35:04Z Test-re-test reliability of two sustained attention tests in persons with chronic stroke Chen H.-C.; Koh C.-L.; CHING-LIN HSIEH; Hsueh I.-P.

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