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Institution	Date	Title	Author
國立交通大學	2014-12-08T15:38:36Z	ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins	Ker, MD; Chang, CY; Chang, YS
國立交通大學	2014-12-08T15:26:36Z	ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins	Ker, MD; Chang, CY; Chang, YS
國立交通大學	2019-08-02T02:18:28Z	ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains	Chen, Jie-Ting; Ker, Ming-Dou
國立交通大學	2017-04-21T06:49:12Z	ESD Protection Design with Latchup-Free Immunity in 120V SOI Process	Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學	2014-12-08T15:38:25Z	ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology	Wang, Chang-Tzu; Ker, Ming-Dou
義守大學	2010-12	ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology	Chang-Tzu Wang;Ming-Dou Ker
國立交通大學	2019-04-02T06:04:53Z	ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications	Ker, Ming-Don; Lin, Chun-Yu; Wu, Yi-Han; Wang, Wen-Tai
國立交通大學	2014-12-08T15:11:24Z	ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers	Ker, Ming-Dou; Chang, Wei-Jen
國立交通大學	2017-04-21T06:55:35Z	ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou
國立交通大學	2017-04-21T06:50:10Z	ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou

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