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Institution	Date	Title	Author
國立交通大學	2019-04-02T05:58:20Z	Gate-induced localized states in graphene: Topological nature in their formation	Wang, L. Y.; Chang, Che-Yuan; Chu, C. S.
臺大學術典藏	2018-09-10T06:02:15Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology	B. Chung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T06:02:16Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique	B. Chung; J. B. Kuo; JAMES-B KUO
國立臺灣大學	2008	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application	Chung, B.; Kuo, J.B.
臺大學術典藏	2018-09-10T07:08:18Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application	JAMES-B KUO; B. Chung; J. B. Kuo
臺大學術典藏	2018-09-10T07:08:19Z	Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications	R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO
國立臺灣海洋大學	2006	Gate-metal formation-related kink effect and gate current on In0.5Al0.5As/In0.5Ga0.5As metamorphic high electron mobility transistor performance	M. K. Hsu;H. R. Chen;S. Y. Chiou;W. T. Chen;G. H. Chen;Y. C. Chang;W. S. Lour
國立臺灣海洋大學	2017	Gate-opening upon CO2 adsorption on a metal–organic framework that mimics a natural stimuli-response system.	T. W. Tseng;L. W. Lee;T. T. Luo;P. H. Chien;Y. H. Liu;S. L. Lee;C. M. Wang;K. L. Lu
國立交通大學	2014-12-08T15:24:59Z	Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes	Chen, Jung-Sheng; Ker, Ming-Dou
國立成功大學	2016-03-15	Gate-Recessed AlGaN/GaN ISFET Urea Biosensor Fabricated by Photoelectrochemical Method	Lee, Ching-Ting; Chiu, Ying-Shuo

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