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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 397586-397595 / 2348973 (共234898页)
<< < 39754 39755 39756 39757 39758 39759 39760 39761 39762 39763 > >>
每页显示[10|25|50]项目
| 國立交通大學 |
2017-04-21T06:48:45Z |
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
|
Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Tseng, Jen-Chou; Jou, Chewn-Pu; Tsai, Ming-Hsien |
| 國立交通大學 |
2019-10-05T00:09:47Z |
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
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Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:18:35Z |
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
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Ker, MD; Chang, WJ |
| 國立交通大學 |
2014-12-08T15:44:57Z |
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
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Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2018-08-21T05:57:09Z |
ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process
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Hung, Tao-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:38:36Z |
ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins
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Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2014-12-08T15:26:36Z |
ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins
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Ker, MD; Chang, CY; Chang, YS |
| 國立交通大學 |
2019-08-02T02:18:28Z |
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains
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Chen, Jie-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:12Z |
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
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Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 義守大學 |
2010-12 |
ESD Protection Design with Lateral DMOS Transistor in 40-V BCD Technology
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Chang-Tzu Wang;Ming-Dou Ker |
显示项目 397586-397595 / 2348973 (共234898页)
<< < 39754 39755 39756 39757 39758 39759 39760 39761 39762 39763 > >>
每页显示[10|25|50]项目
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